Known multi-state storage circuits often incorporate one or more active elements combined with feedback circuitry to produce a plurality of output states. Reliable achievement of an expected output state in response to a set of inputs can be critical to downstream circuit performance.
FIG. 1 illustrates a known realization of an exemplary multi-state storage circuit 10, a D-type flip-flop. The realization of FIG. 1 is a master, M, slave, S, configuration implemented using inverters with a clock input, line 16 and a data input, line 18.
In FIG. 1, inverter 30 provides an inverted clock signal. Circuit elements 34–40 constitute the “master”, M, latch. Circuit elements 44–50 make up the “slave”, S, portion. Together, the master and slave create a positive edge triggered behavior, with respect to clock signals CLK on line 16.
Elements 34 and 40 are known non-inverting transmission or pass gates which resemble switches that are either open circuited or conducting. They are connected in an opposite manner to the CLK or inverted CLK signal such that one element is open and the other is conducting at any given time. This prevents contention at the input of inverter 36.
Elements 36 and 38 are inverters which provide a stable feedback loop 42 when CLK is “high” (logic 1 state). In this case, element 34 is open and 40 is conducting.
When CLK is “low” (logic 0 state), the master stage M is sampling the D input. Element 34 is conducting. Element 40 is open circuited. The slave section S, behaves identically but CLK is driven by an inverted clock signal from inverter 30.
During a critical time when the CLK signal, on line 16, rises, the master M transitions from a transparent to latching state while the slave S goes from the latching to transparent state. For reliable operation, the CLK signal must not rise before the logic state of the D input, line 18, has had enough time to pass through elements 34, 36, and 38. This ensures an orderly transition to the latching state since the output of element 40 will drive the input of inverter 36 with the same logic state that element 34 had been conducting.
A metastable condition can occur when the CLK signal rises before the latest D input state change on line 18 has had time to traverse the feedback loop to the output of inverter 38. In this case, multiple logic states can co-exist in the feedback loop 42 when the master section M enters the latching state. In this instance, the feedback loop 42 forms an oscillator that can ring for an unpredictable amount of time, a metastable state, and resolve to an unpredictable final state.
The length of time that the oscillation will persist is related to the duty cycle distortion experienced by the signal as it completes one circuit through the feedback loop 42. The lower the duty cycle distortion, the longer the oscillation will remain.
For optimal flip-flop performance, designers have used symmetrically balanced inverters and pass gates. In such designs, key flip-flop parameters such as set-up and hold times are equal for both logic 1 and 0 data conditions. Balanced inverters and pass gates also result in low duty cycle distortion in the feedback path. Hence, known flip-flop designs can have very low duty cycle distortion and inadvertently provide feedback paths that can remain in the metastable state for relatively long periods of time relative to the period of the CLK signal. The existence of metastable states in digital circuits is inconsistent with reliable operation of such circuits.
There is thus a continuing need for multi-state circuits which promptly suppress metastable states for a given maximum sampling rate. Preferably such circuits could be fabricated using known techniques so as to avoid having to develop new manufacturing methodologies. Additionally, it would be preferred if such circuits could be implemented with minimal additional components.